calculate_chip_cost

io.github.SiliconAnalysts/silicon-analysts · Verify this server

Pure-function chip cost estimator. Given die dimensions (mm), process node, and optional packaging/HBM parameters, returns: estimatedChipCost (USD), dieArea (mm²), grossDiesPerWafer, frontendYield (%), totalYield (%), and a costBreakdown {waferCostPerGoodDie, packagingAndTestCost, hbmCost, marginCost}. USE THIS for: hypothetical chip cost modeling, sensitivity analysis, fabless tapeout decisions. DO NOT USE for: published cost of an existing accelerator (use get_accelerator_costs); wafer pricing only (use get_wafer_pricing). Required: dieWidth, dieHeight (1–33 mm reticle limit). Errors with INVALID_PARAMS if outside bounds. processNode defaults to tsmc-n5; valid nodes via get_wafer_pricing. Estimates are directional ±15–20%. Optional energy adder: pass energyRegion (texas|ohio|arizona|china|korea|taiwan|germany) to get a conditional `energy` block — regional manufacturing-electricity cost per die (SA estimate; wafer price already embeds foundry energy, so treat it as a scenario delta). energyFacilityOverhead=false drops the ~1.75× facility multiplier. Optional substrate scenario: pass substrate=panel-310x310 to model CoPoS panel-level assembly — applies the midpoint of Yole's realistic 20–30% panel cost-savings band to the packaging cost ONLY (silicon GDPW unchanged; panels are back-end). Conditional `substrateScenario` block + SA-scenario meta note. TSMC CoPoS: pilot ~June 2026, mass production 2028–29 — a forward-looking scenario, not a quote.