pcb_layout

engineer.calc/calc · Verify this server

Turn a SPICE netlist into a fab-ready 2-layer PCB: assigns real footprints (0805, TO-92, DO-35, DIP-8, headers, LED, radial-cap), auto-places components (connectivity-aware; or use your own placement), routes a 2-layer maze router with vias, and VERIFIES the result with DRC (clearance/crossing checks) and ERC (union-find copper connectivity proven against the netlist). Returns the board, routing stats + honest unrouted-net list, DRC violations, ERC net status, a 'manufacturable' flag (true only when DRC+ERC clean and everything routed), SVG layers (top/bottom copper, silkscreen, drill, assembly), and optional Gerber RS-274X + Excellon drill files. Same netlist you simulate with spice_simulate — design, verify, and lay out an entire board through the tool layer. Supply a 'placement' array for production-quality boards; the auto-router is a first-pass best-of-N-seeds.